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4 r on , 4-/8-channel 15 v/+12 v/5 v i cmos multiplexers adg1408/adg1409 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006C2009 analog devices, inc. all rights reserved. features 4.7 maximum on resistance @ 25c 0.5 on resistance flatness up to 190 ma continuous current fully specified at 15 v/+12 v/5 v 3 v logic-compatible inputs rail-to-rail operation break-before-make switching action 16-lead tssop and 4 mm 4 mm lfcsp packages applications relay replacement audio and video routing automatic test equipment data acquisition systems temperature measurement systems avionics battery-powered systems communication systems medical equipment functional block diagram adg1408 s1 s8 d adg1409 s1a s4b da db s4a s1b 1-of-4 decoder 1-of-8 decoder a0 a1 en a0 a1 a2 en 04861-001 figure 1. general description the adg1408/adg1409 are monolithic i cmos? analog multip- lexers comprising eight single channels and four differential channels, respectively. the adg1408 switches one of eight inputs to a common output, as determined by the 3-bit binary address lines, a0, a1, and a2. the adg1409 switches one of four differential inputs to a common differential output, as determined by the 2-bit binary address lines, a0 and a1. an en input on both devices is used to enable or disable the device. when disabled, all channels are switched off. the i cmos (industrial cmos) modular manufacturing process combines high voltage cmos (complementary metal-oxide semiconductor) and bipolar technologies. it enables the devel- opment of a wide range of high performance analog ics capable of 33 v operation in a footprint that no other generation of high voltage parts has been able to achieve. unlike analog ics using conventional cmos processes, i cmos components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. the ultralow on resistance and on resistance flatness of these switches make them ideal solutions for data acquisition and gain switching applications where low distortion is critical. i cmos construction ensures ultralow power dissipation, making the parts ideally suited for portable and battery- powered instruments. product highlights 1. 4 on resistance. 2. 0.5 on resistance flatness. 3. 3 v logic compatible digital input, v ih = 2.0 v, v il = 0.8 v. 4. 16-lead tssop and 4 mm 4 mm lfcsp packages. table 1. related devices part no. description adg1208 / adg1209 low capacitance, low charge injection, and low leakage 4-/8-channel 15 v multiplexers
adg1408/adg1409 rev. b | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 15 v dual supply .......................................................................... 3 12 v single supply ........................................................................ 5 5 v dual supply ............................................................................ 7 continuous current per channel, s or d ...................................8 absolute maximum ratings ............................................................9 thermal resistance .......................................................................9 esd caution...................................................................................9 pin configurations and function descriptions ......................... 10 typical performance characteristics ........................................... 12 terminology .................................................................................... 16 test circuits ..................................................................................... 17 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 20 revision history 3/09rev. a to rev. b change to i dd parameter (table 2) ................................................. 4 change to i dd parameter (table 3) ................................................. 6 8/08rev. 0 to rev. a changes to features .......................................................................... 1 added table 5; renumbered sequentially .................................... 8 changes to table 6 ............................................................................ 9 added exposed pad notation to figure 3 ................................... 10 added exposed pad notation to figure 5 ................................... 11 added exposed pad notation to outline dimensions ............. 19 8/06revision 0: initial version
adg1408/adg1409 rev. b | page 3 of 20 specifications 15 v dual supply v dd = +15 v 10%, v ss = ?15 v 10%, gnd = 0 v, unless otherwise noted. table 2. parameter +25c ?40c to +85c ?40c to +125c 1 unit test conditions/comments analog switch analog signal range v ss to v dd v on resistance (r on ) 4 typ v s = 10 v, i s = ?10 ma; see figure 26 4.7 5.7 6.7 max v dd = +13.5 v, v ss = ?13.5 v on resistance match between 0.2 typ v s = 10 v, i s = ?10 ma channels (r on ) 0.78 0.85 1.1 max on resistance flatness (r flat(on) ) 0.5 typ v s = 10 v, i s = ?10 ma 0.72 0.77 0.92 max leakage currents v dd = +16.5 v, v ss ?16.5 v = source off leakage, i s (off ) 0.04 na typ v s = 10 v, v d = 10 v; see ? figure 27 0.2 0.6 5 na max drain off leakage, i d (off ) 0.04 na typ v s = 10 v, v d = ? 10 v; see figure 27 0.45 2 30 na max channel on leakage, i d , i s (on) 0.1 na typ v s = v d = 10 v; see figure 28 1.5 3 30 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current 0.005 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 4 pf typ dynamic characteristics 2 transition time, t transition 140 ns typ r l = 100 , c l = 35 pf 170 210 240 ns max v s = 10 v, see figure 29 break-before-make time delay, t bbm 50 ns typ r l = 100 , c l = 35 pf 30 ns min v s1 = v s2 = 10 v; see figure 30 t on (en) 100 ns typ r l = 100 , c l = 35 pf 120 150 165 ns max v s = 10 v; see figure 31 t off (en) 100 ns typ r l = 100 , c l = 35 pf 120 150 170 ns max v s = 10 v; see figure 31 charge injection ?50 pc typ v s = 0 v, r s = 0 , c l = 1 nf; see figure 32 off isolation ?70 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 33 channel-to-channel crosstalk ?70 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 34 total harmonic distortion, thd + n 0.025 % typ r l = 110 , 15 v p-p, f = 20 hz to 20 khz; see figure 36 ?3 db bandwidth r l = 50 , c l = 5 pf; see figure 35 adg1408 60 mhz typ adg1409 115 mhz typ insertion loss 0.24 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 35 c s (off ) 14 pf typ f = 1 mhz c d (off) adg1408 80 pf typ f = 1 mhz adg1409 40 pf typ f = 1 mhz c d , c s (on) adg1408 135 pf typ f = 1 mhz adg1409 90 pf typ f = 1 mhz
adg1408/adg1409 rev. b | page 4 of 20 parameter +25c ?40c to +85c ?40c to +125c 1 unit test conditions/comments power requirements v dd = +16.5 v, v ss = ?16.5 v i dd 0.002 a typ digital inputs = 0 v or v dd 1 a max 220 a typ digital inputs = 5 v 380 a max i ss 0.002 a typ digital inputs = 0 v, 5 v or v dd 1 a max v dd /v ss 4.5/16.5 v min/max 1 temperature range: y ve rsion: ?40c to +125c. 2 guaranteed by design, not subject to production test.
adg1408/adg1409 rev. b | page 5 of 20 12 v single supply v dd = 12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 3. parameter +25c ?40c to +85c ?40c to +125c 1 unit test conditions/comments analog switch analog signal range 0 to v dd v on resistance (r on ) 6 typ v s = 0 v to 10 v, i s = ?10 ma; see figure 26 8 9.5 11.2 max v dd = 10.8 v, v ss = 0 v on resistance match 0.2 typ v s = 0 v to 10 v, i s = ?10 ma between channels (r on ) 0.82 0.85 1.1 max on resistance flatness (r flat(on) ) 1.5 typ v s = 0 v to 10 v, i s = ?10 ma 2.5 2.5 2.8 max leakage currents v dd = 13.2 v source off leakage, i s (off ) 0.04 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 27 0.2 0.6 5 na max drain off leakage, i d (off ) 0.04 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 27 0.45 1 37 na max channel on leakage, i d , i s (on) 0.06 na typ v s = v d = 1 v or 10 v; see figure 28 0.44 1.3 32 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current 0.005 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 5 pf typ dynamic characteristics 2 transition time, t transition 200 ns typ r l = 100 , c l = 35 pf 260 330 380 ns max v s = 8 v; see figure 29 break-before-make time delay, t bbm 90 ns typ r l = 100 , c l = 35 pf 40 ns min v s1 = v s2 = 8 v; see figure 30 t on (en) 160 ns typ r l = 100 , c l = 35 pf 210 250 285 ns max v s = 8 v; see figure 31 t off (en) 115 ns typ r l = 100 , c l = 35 pf 145 180 200 ns max v s = 8 v; see figure 31 charge injection ?12 pc typ v s = 6 v, r s = 0 , c l = 1 nf; see figure 32 off isolation ?70 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 33 channel-to-channel crosstalk ?70 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 34 ?3 db bandwidth r l = 50 , c l = 5 pf; see figure 35 adg1408 36 mhz typ adg1409 72 mhz typ insertion loss 0.5 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 35 c s (off ) 25 pf typ f = 1 mhz c d (off) adg1408 165 pf typ f = 1 mhz adg1409 80 pf typ f = 1 mhz c d , c s (on) adg1408 200 pf typ f = 1 mhz adg1409 120 pf typ f = 1 mhz
adg1408/adg1409 rev. b | page 6 of 20 parameter +25c ?40c to +85c ?40c to +125c 1 unit test conditions/comments power requirements v dd = 13.2 v i dd 0.002 a typ digital inputs = 0 v or v dd 1 a max 220 a typ digital inputs = 5 v 380 a max v dd 5/16.5 v min/max v ss = 0 v, gnd = 0 v 1 temperature range for y ve rsion: ?40c to +125c. 2 guaranteed by design, not subject to production test.
adg1408/adg1409 rev. b | page 7 of 20 5 v dual supply v dd = +5 v 10%, v ss = ?5 v 10%, gnd = 0 v, unless otherwise noted. table 4. parameter +25c ?40c to +85c ?40c to +125c 1 unit test conditions/comments analog switch analog signal range v ss to v dd v on resistance (r on ) 7 typ v s = 4.5 v, i s = ?10 ma; see figure 26 9 10.5 12 max v dd = +4.5 v, v ss = ?4.5 v on resistance match between 0.3 typ v s = 4.5 v, i s = ?10 ma channels (r on ) 0.78 0.91 1.1 max on resistance flatness (r flat(on) ) 1.5 typ v s = 4.5 v; i s = ?10 ma 2.5 2.5 3 max leakage currents v dd = +5.5 v, v ss ?5.5 v = source off leakage, i s (off ) 0.02 na typ v s = 4.5 v, v d = 4.5 v; see ? figure 27 0.2 0.6 5 na max drain off leakage, i d (off ) 0.02 na typ v s = 4.5 v, v d = ? 4.5 v; see figure 27 0.45 0.8 20 na max channel on leakage, i d , i s (on) 0.04 na typ v s = v d = 4.5 v; see figure 28 0.3 1.1 22 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current 0.005 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 5 pf typ dynamic characteristics 2 transition time, t transition 330 ns typ r l = 100 , c l = 35 pf 440 530 550 ns max v s = 5 v; see figure 29 break-before-make time delay, t bbm 100 ns typ r l = 100 , c l = 35 pf 50 ns min v s1 = v s2 = 5 v; see figure 30 t on (en) 245 ns typ r l = 100 , c l = 35 pf 330 400 440 ns max v s = 5 v; see figure 31 t off (en) 215 ns typ r l = 100 , c l = 35 pf 285 335 370 ns max v s = 5 v; see figure 31 charge injection C10 pc typ v s = 0 v, r s = 0 , c l = 1 nf; see figure 32 off isolation C70 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 33 channel-to-channel crosstalk C70 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 34 total harmonic distortion, thd + n 0.06 % typ r l = 110 , 5 v p-p, f = 20 hz to 20 khz; see figure 36 ?3 db bandwidth r l = 50 , c l = 5 pf; see figure 35 adg1408 40 mhz typ adg1409 80 mhz typ insertion loss 0.5 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 35 c s (off ) 20 pf typ f = 1 mhz c d (off) adg1408 130 pf typ f = 1 mhz adg1409 65 pf typ f = 1 mhz c d , c s (on) adg1408 180 pf typ f = 1 mhz adg1409 120 pf typ f = 1 mhz
adg1408/adg1409 rev. b | page 8 of 20 parameter +25c ?40c to +85c ?40c to +125c 1 unit test conditions/comments power requirements v dd = +5.5 v, v ss = ?5.5 v i dd 0.001 a typ digital inputs = 0 v or v dd 1 a max i ss 0.001 a typ digital inputs = 0 v, 5 v or v dd 1 a max v dd /v ss 4.5/16.5 v min/max 1 temperature range for y ve rsion: ?40c to +125c. 2 guaranteed by design, not subject to production test. continuous current per channel, s or d table 5. parameter 25c 85c 125c unit test conditions/comments continuous current, s or d 1 15 v dual supply v dd = +13.5 v, v ss = ?13.5 v adg1408 190 105 50 ma max adg1409 140 85 45 ma max 12 v single supply v dd = 10.8 v, v ss = 0 v adg1408 160 95 50 ma max adg1409 120 75 40 ma max 5 v dual supply v dd = +4.5 v, v ss = ?4.5 v adg1408 155 90 45 ma max adg1409 115 70 40 ma max 1 guaranteed by design, not subject to production test.
adg1408/adg1409 rev. b | page 9 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. table 6. parameter rating v dd to v ss 35 v v dd to gnd ?0.3 v to +25 v v ss to gnd +0.3 v to ?25 v analog inputs, digital inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first continuous current, s or d table 5 data + 10% peak current, s or d (pulsed at 1 ms, 10% duty cycle maximum) 350 ma operating temperature range industrial (y version) ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c reflow soldering peak temperature (pb-free) 260(+0/?5)c 1 overvoltages at a, en, s, or d are cl amped by internal diodes. current should be limited to the maximum ratings given. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating can be applied at any one time. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 7. thermal resistance package type ja jc unit 16-lead tssop 150.4 50 c/w 16-lead lfcsp 30.4 c/w esd caution
adg1408/adg1409 rev. b | page 10 of 20 pin configurations and function descriptions 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 en v ss s1 s4 s3 s2 a0 a2 gnd v dd s7 ds s6 s5 a1 adg1408 top view (not to scale) 8 0 4861-002 figure 2. adg1408 pin configuration (tssop) pin 1 indicator 1v ss notes 1. the exposed pad is connected internally. for increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, v ss . 2 s1 3 s2 4 s3 11 v dd 12 gnd 10 s5 9s6 5 s 4 6 d 7 s 8 8 s 7 1 5 a 0 1 6 e n 1 4 a 1 1 3 a 2 top view (not to scale) adg1408 04861-003 figure 3. adg1408 pin configuration (lfcsp) table 8. adg1408 pin function descriptions pin no. tssop lfcsp mnemonic description 1 15 a0 logic control input. 2 16 en active high digital input. when low, the device is disabled and all switches are off. when high, ax logic inputs determine on switches. 3 1 v ss most negative power supply potential. in single supply applications, it can be connected to ground. 4 2 s1 source terminal 1. can be an input or an output. 5 3 s2 source terminal 2. can be an input or an output. 6 4 s3 source terminal 3. can be an input or an output. 7 5 s4 source terminal 4. can be an input or an output. 8 6 d drain terminal. can be an input or an output. 9 7 s8 source terminal 8. can be an input or an output. 10 8 s7 source terminal 7. can be an input or an output. 11 9 s6 source terminal 6. can be an input or an output. 12 10 s5 source terminal 5. can be an input or an output. 13 11 v dd most positive power supply potential. 14 12 gnd ground (0 v) reference. 15 13 a2 logic control input. 16 14 a1 logic control input. ep exposed pad the exposed pad is connected internally. for in creased reliability of the solder joints and maximum thermal capability, it is recommended th at the pad be soldered to the substrate, v ss . table 9. adg1408 truth table a2 a1 a0 en on switch x x x 0 none 0 0 0 1 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 8
adg1408/adg1409 rev. b | page 11 of 20 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 en v ss s1a s4a s3a s2a a0 gnd v dd s1b s4b da db s3b s2b a1 adg1409 top view (not to scale) 0 4861-004 figure 4. adg1409 pin configuration (tssop) pin 1 indicator 1v ss 2 s1a 3 s2a 4 s3a 11 s1b 12 v dd 10 s2b 9s3b 5 s 4 a 6 d a 7 d b 8 s 4 b 1 5 a 0 1 6 e n 1 4 a 1 1 3 g n d top view (not to scale) adg1409 04861-005 notes 1. the exposed pad is connected internally. for increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, v ss . figure 5. adg1409 pin configuration (lfcsp) table 10. adg1409 pin function descriptions pin no. tssop lfcsp mnemonic description 1 15 a0 logic control input. 2 16 en active high digital input. when low, the device is disabled and all switches are off. when high, ax logic inputs determine on switches. 3 1 v ss most negative power supply potential. in single supply applications, it can be connected to ground. 4 2 s1a source terminal 1a. ca n be an input or an output. 5 3 s2a source terminal 2a. ca n be an input or an output. 6 4 s3a source terminal 3a. ca n be an input or an output. 7 5 s4a source terminal 4a. ca n be an input or an output. 8 6 da drain terminal a. can be an input or an output. 9 7 db drain terminal b. can be an input or an output. 10 8 s4b source terminal 4b. ca n be an input or an output. 11 9 s3b source terminal 3b. ca n be an input or an output. 12 10 s2b source terminal 2b. can be an input or an output. 13 11 s1b source terminal 1b. can be an input or an output. 14 12 v dd most positive power supply potential. 15 13 gnd ground (0 v) reference. 16 14 a1 logic control input. ep exposed pad the exposed pad is connected internally. for increa sed reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, v ss . table 11. adg1409 truth table a1 a0 en on switch pair x x 0 none 0 0 1 1 0 1 1 2 1 0 1 3 1 1 1 4
adg1408/adg1409 rev. b | page 12 of 20 typical performance characteristics 5 6 0 ?16.5 15.5 source or drain voltage (v) on resistance ( ? ) 04861-006 4 3 2 1 ?12.5 ?8.5 ?4.5 ?0.5 3.5 7.5 11.5 v dd = +15v, v ss = ?15v v dd = +13.5v, v ss = ?13.5v v dd = +12v, v ss = ?12v v dd = +10v, v ss = ?10v v dd = +16.5v, v ss = ?16.5v t a = 25c figure 6. on resistance vs. v d , v s ; dual supply 5 9 6 7 8 0 ?7 ?4?5?6 7 source or drain voltage (v) on resistance ( ? ) 04861-036 4 3 2 1 ?3 ?2 ?1 0 5 43 12 6 v dd = +7v, v ss = ?7v v dd = +5.5v, v ss = ?5.5v v dd = +5v, v ss = ?5v v dd = +4.5v, v ss = ?4.5v t a = 25c figure 7. on resistance vs. v d , v s ; dual supply 12 13 0 0 source or drain voltage (v) on resistance ( ? ) 04861-007 11 10 9 8 7 6 5 4 3 2 1 12345678910111213 v dd = 12v v dd = 13.2v v dd = 10.8v v dd = 8v v dd = 5v t a = 25c v ss = 0v figure 8. on resistance vs. v d , v s ; single supply 7 0 ?15 source or drain voltage (v) on resistance ( ? ) 04861-008 15 t a = +25c t a = +85c t a = ?40c t a = +125c v dd = +15v v ss = ?15v 6 5 4 3 2 1 ?10 ?5 0 5 10 figure 9. on resistance vs. v d , v s for different temperatures; 15 v dual supply 12 0 ?5 source or drain voltage (v) on resistance ( ? ) 04861-009 5 10 8 6 4 2 ?4 ?3 ?2 ?1 0 1 2 3 4 t a = +25c t a = +85c t a = ?40c t a = +125c v dd = +5v v ss = ?5v figure 10. on resistance vs. v d , v s for different temperatures; 5 v dual supply 10 0 0 source or drain voltage (v) on resistance ( ? ) 04861-010 12 9 8 7 6 5 4 3 2 1 246810 t a = +25c t a = +85c t a = ?40c t a = +125c v dd = 12v v ss = 0v figure 11. on resistance vs. v d , v s for different temperatures; 12 v single supply
adg1408/adg1409 rev. b | page 13 of 20 1.0 ?1.0 0 temperature (c) leakage current (na) 04861-011 80 i s (off) +? i d (off) +? i s (off) ?+ i d (off) ?+ i d, i s (on) ++ i d, i s (on) ?? v dd = +15v v ss = ?15v v bias = +10v/?10v 0.8 0.6 0 0.2 0.4 ?0.2 ?0.4 ?0.6 ?0.8 10 20 30 40 50 60 70 figure 12. leakage current vs. temperature; 15 v dual supply 14 ?4 0 temperature (c) leakage current (na) 04861-012 120 i s (off) +? i d (off) +? i s (off) ?+ i d (off) ?+ i d, i s (on) ++ i d, i s (on) ?? v dd = +15v v ss = ?15v v bias = +10v/?10v 8 10 12 4 6 2 0 ?2 20 40 60 80 100 figure 13. leakage current vs. temperature; 15 v dual supply 10 ?1 0 temperature (c) leakage current (na) 04861-015 120 i s (off) +? i d (off) +? i s (off) ?+ i d (off) ?+ i d, i s (on) ++ i d, i s (on) ?? v dd = +5v v ss = ?5v v bias = +4.5v/?4.5v 9 8 7 4 5 6 3 2 1 0 20 40 60 80 100 figure 14. leakage current vs. temperature; 5 v dual supply 18 16 ?2 0 temperature (c) leakage current (na) 04861-013 120 i s (off) +? i d (off) +? i s (off) ?+ i d (off) ?+ i d, i s (on) ++ i d, i s (on) ?? v dd = 12v v ss = 0v v bias = 1v/10v 10 12 14 6 8 4 2 0 20 40 60 80 100 figure 15. leakage current vs. temperature; 12 v single supply 70 0 01 logic, ax (v) i dd (a) 4 60 50 40 30 20 10 2 4 6 8 10 12 v dd = +15v v ss = ?15v v dd = +12v v ss = 0v v dd = +5v v ss = ?5v i dd per channel t a = 25c 04861-034 figure 16. positive supply current vs. logic level 200 ?200 ?15 15 v s (v) charge injection (pc) t a = 25c 150 100 50 0 ?50 ?100 ?150 ?10 ?5 0 5 10 v dd = +15v v ss = ?15v v dd = +12v v ss = 0v v dd = +5v v ss = ?5v 04861-014 figure 17. charge injection vs. source voltage
adg1408/adg1409 rev. b | page 14 of 20 450 0 ?40 120 temperature (c) time (ns) 400 350 300 250 200 150 100 50 ?20 0 20 40 60 80 100 v dd = +15v v ss = ?15v v dd = 12v v ss = 0v v dd = +5v v ss = ?5v 04861-033 figure 18. transition time vs. temperature 0 ?110 1k 1g frequency (hz) off isolation (db) ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10k 100k 1m 10m 100m v dd = +15v v ss = ?15v t a = 25c 04861-016 figure 19. off isol ation vs. frequency 0 ?110 1k 1g frequency (hz) crosstalk (db) ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10k 100k 1m 10m 100m v dd = +15v v ss = ?15v t a = 25c 04861-017 figure 20. adg1408 crosstalk vs. frequency 0 ?110 1k 1g frequency (hz) crosstalk (db) ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10k 100k 1m 10m 100m v dd = +15v v ss = ?15v t a = 25c adjacent channel nonadjacent channel 04861-018 figure 21. adg1409 crosstalk vs. frequency 0 ?4.0 100 100m frequency (hz) bandwidth (db) 1k 10k 100k 1m 10m v dd = +15v v ss = ?15v t a = 25c ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 ?3.0 ?3.5 04861-019 figure 22. adg1408 on response vs. frequency 0 ?4.0 100 1g 100m frequency (hz) bandwidth (db) 1k 10k 100k 1m 10m v dd = +15v v ss = ?15v t a = 25c ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 ?3.0 04861-031 ?3.5 figure 23. adg1409 on response vs. frequency
adg1408/adg1409 rev. b | page 15 of 20 0 10 100k frequency (hz) thd + n (%) 0.09 0.10 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 100 1k 10k load = 110 ? t a = 25c v dd = +5v, v ss = ?5v, v s = +5v p-p v dd = +15v, v ss = ?15v, v s = +15v p-p 04861-032 figure 24. total harmonic distortion plus noise vs. frequency 0 ?110 100 1k 10m frequency (hz) acpsrr (db) ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10k 100k 1m v dd = +15v v ss = ?15v t a = 25c v p-p = 0.63v 04861-035 no decoupling capacitors decoupling capacitors on supplies figure 25. ac power supply re jection ratio vs. frequency
adg1408/adg1409 rev. b | page 16 of 20 terminology r on ohmic resistance between d and s. r on difference between the r on of any two channels. r flat(on) flatness is defined as the difference between the maximum and minimum value of on resistance as measured. i s (off) source leakage current when the switch is off. i d (off) drain leakage current when the switch is off. i d , i s (on) channel leakage current when the switch is on. v d (v s ) analog voltage on terminal d and terminal s. c s (off) channel input capacitance for off condition. c d (off) channel output capacitance for off condition. c d , c s (on) on switch capacitance. c in digital input capacitance. t on (en) delay time between the 50% and 90% points of the digital input and switch on condition. t off (en) delay time between the 50% and 90% points of the digital input and switch off condition. t transition delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. t bbm off time measured between the 80% point of both switches when switching from one address state to another. v inl maximum input voltage for logic 0. v inh minimum input voltage for logic 1. i inl , i inh input current of the digital input. i dd positive supply current. i ss negative supply current. off isolation a measure of unwanted signal coupling through an off channel. charge injection a measure of the glitch impulse transferred from the digital input to the analog output during switching. bandwidth frequency at which the output is attenuated by 3 db. on response frequency response of the on switch. total harmonic distortion plus noise (thd + n) ratio of the harmonic amplitude plus noise of the signal to the fundamental. ac power supply rejection ratio (acpsrr) a measure of the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. the dc voltage on the device is modulated by a sine wave of 0.62 v p-p. the ratio of the amplitude of signal on the output to the amplitude of the modulation is the acpsrr.
adg1408/adg1409 rev. b | page 17 of 20 test circuits i ds sd v s v 04861-020 figure 26. on resistance sd v s a a v d i s (off) i d (off) 04861-021 figure 27. off leakage sd a v d i d (on) nc nc = no connect 04861-022 figure 28. on leakage 3v 0v output t r < 20ns t f < 20ns address drive (v in ) t transition t transition 50% 50% 90% 90% output adg1408 1 a0 a1 a2 50? 100? gnd s1 s2 to s7 s8 d 35pf v in 2.4v en v dd v ss v dd v ss v s1 v s8 1 similar connection for adg1409. 04861-023 figure 29. address to ou tput switching times, t transition output adg1408 1 a0 a1 a2 50 ? 100 ? gnd s1 s2 to s7 s8 d 35pf v in 2.4v en v dd v ss v dd v ss v s 1 similar connection for adg1409. 3v 0v output 80% 80% a ddress drive (v in ) t bbm 04861-024 figure 30. break-before-make delay, t bbm output adg1408 1 a0 a1 a2 50 ? 100? gnd s1 s2 to s8 d 35pf v in en v dd v ss v dd v ss v s 1 similar connection for adg1409. 3v 0v output 50% 50% t off (en) t on (en) 0.9v o 0.9v o enable drive (v in ) 04861-025 figure 31. enable delay, t on (en), t off (en)
adg1408/adg1409 rev. b | page 18 of 20 3v v in v out q inj = c l v out v out d s en gnd c l 1nf v out v in r s v s v dd v ss v dd v ss a0 a1 a2 adg1408 1 1 similar connection for adg1409. 04861-026 figure 32. charge injection v out 50? network analyzer r l 50? s d 50? off isolation = 20 log v out v s v s v dd v ss 0.1f v dd 0.1f v ss gnd 04861-027 figure 33. off isolation channel-to-channel crosstalk = 20 log v out gnd s1 d s2 v out network analyzer r l 50? r 50? v s v s v dd v ss 0.1f v dd 0.1f v ss 04861-028 figure 34. channel-to-channel crosstalk v out 50? network analyzer r l 50 ? s d insertion loss = 20 log v out with switch v out without switch v s v dd v ss 0.1f v dd 0.1f v ss gnd 04861-029 figure 35. insertion loss v out r s audio precision r l 10k ? in v in s d v s v p-p v dd v ss 0.1f v dd 0.1f v ss gnd 04861-030 figure 36. thd + noise
adg1408/adg1409 rev. b | page 19 of 20 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 37. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters compliant to jedec standards mo-220-vggc. 1 0.65 bsc 0.60 max p i n 1 i n d i c a t o r 1.95 bcs 0.50 0.40 0.30 0.25 min 3.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indi c ator coplanarity 0.08 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 4.00 bsc sq 2.65 2.50 sq 2.35 16 5 13 8 9 12 4 exposed pa d bottom view 031006-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 38. 16-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm, very thin quad (cp-16-13) dimensions shown in millimeters
adg1408/adg1409 rev. b | page 20 of 20 ordering guide model temperature range package description package option adg1408yruz 1 ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 adg1408yruz-reel 1 ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 adg1408yruz-reel7 1 ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 adg1408ycpz-reel7 1 ?40c to +125c 16-lead lead frame chip scale package [lfcsp_vq] cp-16-13 adg1409yruz 1 ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 adg1409yruz-reel 1 ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 adg1409yruz-reel7 1 ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 ADG1409YCPZ-REEL7 1 ?40c to +125c 16-lead lead frame chip scale package [lfcsp_vq] cp-16-13 1 z = rohs compliant part. ?2006C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d04861-0-3/09(b)

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